1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a memory device with pseudo double clock signals and the method using the same.
2. Description of the Related Art
Traditionally, a dynamic random access memory (DRAM) is a memory device with an asynchronous interface with input control signals. That is, a DRAM device responds to changes in input signals as quickly as possible. However, the pipelining instructions cannot be applied to a DRAM device due to its asynchronous characteristic. Accordingly, a synchronous dynamic random access memory (SDRAM) device with synchronous interface was introduced. An SDRAM device waits for a clock signal before responding to input control signals and is therefore synchronized with a computer's system bus. An SDRAM device utilizes a finite state machine driven by a clock signal to pipeline input instructions.
With the pipelining technique utilized, an SDRAM device is able to accept a new instruction before finishing processing a previously accepted instruction. In a write operation, the write instruction can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a read operation, the requested data appears after a fixed number of clock pulses, and additional instructions can be sent after the read instruction. This kind of delay is called latency and is an important parameter to consider when evaluating the performance of an SDRAM device.
While the access latency of a DRAM device is limited by the DRAM array, to exploit the bandwidth potential of a DRAM device and thus reduce the latency of an SDRAM device, a double data rate (DDR) SDRAM device was introduced. A DDR SDRAM device transfers data on both the rising edge and the falling edge of a clock signal, and thus achieves nearly twice the bandwidth of a traditional SDRAM device with a single data rate. The typical clock rates of a DDR SDRAM device are 100, 133, 166 and 200 MHz.
With the development of memory device technology, a more advanced memory device, DDR2 SDRAM, was introduced. A DDR2 SDRAM device doubles the clock rate of a traditional DDR SDRAM. That is, the typical clock rates of a DDR2 SDRAM device are 200, 266, 333 and 400 MHz.
To meet the clock rate requirement of DDR2 SDRAM standard, the memory controller and other circuit components such as the sense amplifier, row decoder and column decoder may require a redesign, which is a complicated and time consuming process. In addition, the original circuit designs for DDR SDRAM devices may need to be abandoned, which reduces the profit generated from the investment in the design for DDR SDRAM devices. However, in some circumstances, even if a DDR2 SDRAM clock rate is required, a typical DDR SDRAM device may suffice for the system design. In such circumstances, utilizing a DDR2 SDRAM device merely to meet a requirement of the specification may not be cost effective. Therefore, there is a need to design a method for applying an input clock signal to a memory device, wherein the clock rate of the input clock signal is two times that of the memory device, such that a typical DDR SDRAM device can operate under the DDR2 SDRAM clock rate.